Data storage systems can include two storage processors for handling the data processing and caching operations of the storage system. The two storage processors enable the system to perform up to twice as much work in parallel than a single processor and enable the system to be cache-enabled. Write data that is processed by the storage processors is eventually written to disk drives in the disk drive array. However, because the process of writing data to a disk drive takes much longer than the amount of time required by the storage processor to process incoming data, the data is stored in cache memory before it is finally written to the disk drive. This type of data is called write cache data because it is in the process of being written to the disk drive, but has not yet been written to the disk drive.
Both storage processors process data read and write commands for the system concurrently. In order to prevent a loss of all write cache data stored in the cache memory associated with a particular processor in the event that the particular processor becomes unavailable or fails, the write cache data is stored in the cache memories associated with both storage processors through a mechanism called mirroring. Data mirroring involves providing an exact copy of all data on each storage processor's cache memory to the cache memory of the other storage processor. This is done so that, at any point in time, the cache memories associated with each storage processor are exactly the same. In the event that one of the storage processors should fail, none of its write cache data is lost, because it has been stored on the “peer” storage processor with which the failed storage processor cooperates. The communication between storage processors can be configured according to a number of different protocols, such as PCI-Express, which is a low-voltage differential signaling protocol.
When a storage processor is powered up, it must perform a discovery operation to ascertain what devices are configured in the system with which it is associated so that it can configure the devices into its memory space. However, when two or more storage processors are connected to communicate with each other, it is important that each storage processor be able to enumerate its associated memory space upon power-up without attempting to enumerate the memory space associated with its peer. Transparent bridges are typically used to connect the root complex associated with each storage processor to downstream devices in a way that enables the storage processor to include the downstream devices in its enumeration process. The use and operation of transparent bridges for this purpose is known in the art.
In order to prevent one storage processor from enumerating devices that are associated with the peer storage processor, the communication link between the storage processors utilize non-transparent bridges. As is known in the art, non-transparent bridges enable data transactions to be forwarded from one side of the non-transparent bridge to the other, however, to the storage processors on either side of the non-transparent bridge, the non-transparent bridge appears to be an endpoint to the discovery and configuration software of each storage processor. This eliminates the possibility of one storage processor enumerating devices that are associated with its peer. While both transparent and non-transparent bridges provide a path between two independent data buses, in the case of a non-transparent bridge, devices on the downstream side of a non-transparent bridge are not visible from the upstream side of the non-transparent bridge. The use and operation of non-transparent bridges for this purpose is known in the art.
FIG. 1 is a schematic diagram of a prior art data processing system 100 that utilizes transparent and non-transparent bridges. The system 100 includes a first data processing device 120a and a second data processing device 120b. Data processing devices 120a and 120b are identically configured, thus enabling the design and manufacture of a single part, to reduce development and manufacturing costs. Each data processing device 120a, 120b includes a storage processor 102a, 102b, which controls the operation of the data processing device. A root complex 104a, 104b is connected between the storage processor 102a, 102b and a switch device 106a, 106b. In a PCI-Express-protocol system, the root complex 104a, 104b is the PCI-Express version of a Northbridge, which transmits data between the storage processor 102a, 102b and the switch 106a, 106b. Each switch 106a, 106b includes a number of transparent bridges 110a–110f. As Shown in FIG. 1, in the case of switch 106a, transparent bridge 110a is coupled to root complex 104a to enable the transmission of data to and from the root complex 104a. Transparent bridge 110b is connected between transparent bridge 110a and an end point device 108a for enabling the transmission of data to and from the end point device 108a and transparent bridge 110c is connected between transparent bridge 110a and an end point device 108b for enabling the transmission of data to and from the end point device 108b. The configuration of transparent bridges 110d–110f in switch 106b is identical to that of transparent bridges 110a–110c of switch 106a. Transparent bridges 110d–110f enable the transmission of data to and from root complex 104b, end point device 108c and end point device 108d, respectively.
Switches 106a, 106b each also include a non-transparent bridge 114a, 114b coupled between transparent bridge 110a, 110b, respectively, and the midplane 116. As discussed above, the non-transparent bridges 114a, 114b enable communications between the data processing devices 120a and 120b while blocking the downstream elements from the discovery and configuration software of the upstream storage processor.
Upon power-up, each storage processor 102a, 102b begins enumerating to determine the topology. The processor will pass through the root complex 104a, 104b and enter the switch 106a, 106b. It will then enter the transparent bridge 110a, 110b. Since the bridge is transparent, the storage processor will continue to enumerate. The storage processor 102a, 102b will pass through transparent bridges 110b, 110c; 110e, 110f and will discover end points 108a, 108b; 108c, 108d. Upon discovering the endpoints, the storage processor does not explore further along that path. The storage processor 102a, 102b then reaches non-transparent bridge 114a, 114b. The storage processor detects the non-transparent bridge 114a, 114b as an end point and explores no further from that point. The storage processor reads the base address register (BAR) of the non-transparent bridge to determine the memory requirements for windows into the memory space on the downstream side of the non-transparent bridge 114a, 114b. The memory space requirements can be preloaded from an EEPROM (not shown) into the BAR Setup Registers of the non-transparent bridge 114a, 114b. 
As shown in FIG. 1, the switch 106a, 106b, utilizing the PCI-Express protocol, includes 24 lanes of communication, including eight lanes for each of transparent bridges 110b, 110c; 110e, 110f and eight lanes for the non-transparent bridge 114a, 114b. All eight lanes pass through the non-transparent bridges 114a, 114b to connect the storage processing devices at the midplane 116. Therefore, any data transmitted from one storage processor to the other must pass through two non-transparent bridges, which increases the latency of the system. Furthermore, the cost, size and complexity of the switch is increased because of the additional hardware required for two full eight lane non-transparent bridges.